300MHz,
1.50ns to 99.9ms width,
1% to 90% duty cycle,
1ns variable transitions,
10ps timing resolution,
100mV to 5Vpp and 10mV resolution in amplitude,
Data and clock simulation, Glitch testing,
Period 3.33ns to 99.9ms, Delay 0.00ns to 99.9ms,
Double pulses 3.33ns to 99.9ms,
width 1.50ns to 99.9ms,
Duty cycle 1% to 90%,
Transition time 1ns to 100us,
Output : High level -4.90V to +5.00V
             Low level -5.00V to +4.90V
Amplitude 100mV to 5Vpp